A type of commercially available flash memory product is a MirrorBit® memory device available from Spansion, LLC, located in Sunnyvale, Calif. A MirrorBit cell effectively doubles the intrinsic density of a flash memory array by storing two physically distinct bits on opposite sides of a memory cell. Each bit within a cell can be programmed with a binary unit of data (either a logic one or zero) that is mapped directly to the memory array.
A portion of an exemplary MirrorBit® memory device 10, illustrated in FIG. 1, includes a P-type semiconductor substrate 12 within which are formed spaced-apart source/drain regions 14, 16 respectively (both typically having N-type conductivity), otherwise known as bitline regions or bitlines. A charge trapping stack 18 is disposed on the top surface of the substrate between the bitlines. The charge trapping stack 18 typically comprises, for example, a charge trapping layer, often a silicon nitride layer 20, disposed between a first or bottom insulating layer 22, such as a silicon dioxide layer (commonly referred to as a tunnel oxide layer), and a second or top insulating layer 24. A gate electrode 26, which typically comprises an N or N+ polycrystalline silicon layer, is formed over the charge trapping stack. An isolation region or gate insulator 40 divides the charge trapping stack below each gate electrode 26 to form a first charge storage node or bit 28 and a complementary second charge storage node or bit 30 of memory cells 32 and 34.
As devices densities increase and product dimensions decrease, it is desirable to reduce the size of the various structures and features associated with individual memory cells, sometimes referred to as scaling. However, the fabrication techniques used to produce flash memory arrays limit or inhibit the designer's ability to reduce device dimensions. For example, with 65 nm node devices, it is not necessary to isolate portions of the charge trapping layer of complimentary bits, that is, gate insulators 40 in cells 32 and 34 are not necessary. However, as device dimensions decrease to 45 nm nodes, isolation of the charge trapping layer portions of the complimentary nodes by gate insulator 40 becomes advantageous. In addition, it is difficult to achieve the desired charge trapping stack thickness in the charge storage nodes independently of the thickness of the gate insulator separating the storage nodes. Further, as charge storage nodes become narrower, variations in the length of the nodes have more deleterious effects on the charge storage characteristics of the nodes. Moreover, charge storage nodes fabricated with less than substantially vertical sidewalls can result in “shadowing” that effect subsequent etching processes.
Accordingly, it is desirable to provide methods of fabricating dual bit memory devices with design flexibility. In addition, it is desirable to provide methods of fabricating flash memory devices that can be scaled with device dimensions. It is also desirable to provide memory devices with substantially vertical sidewalls. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.